The present invention relates generally to semiconductor device structures and semiconductor processing in integrated circuits and, more particularly, to programmable interconnect devices (PIDs) and method of manufacturing same.
A PID is one type of an antifuse structure. An antifuse structure is a device which operates, as the name implies, in the opposite manner of a fuse. If it is unprogrammed, i.e., prior to the application of a programming voltage, the antifuse forms a high resistance, or open electrical path. If the antifuse structure is programmed by applying a critical voltage across it, it forms a low resistance, or closed electrical path between two conducting lines.
In integrated circuits, multiple layers of interconnecting conducting lines are stacked over each other. Multi-layer interconnect structures are formed with insulating layers between the conducting lines. Typically, to form an antifuse structure between first and second lowest conducting layers, the first conducting layer is covered with a thick insulating layer. This first conducting layer may be a doped region in the integrated circuit substrate, a doped region of an epitaxial layer on the substrate, or a doped polycrystalline silicon layer over the substrate. Then, a contact opening is formed through the thick insulating layer where the interconnection is desired. A dielectric antifuse layer is deposited over the thick insulating layer and the contact opening. The important parameters of an antifuse structure largely depend on the material used for this dielectric layer. Then, the second conducting layer is deposited over the dielectric layer. By standard semiconductor processing techniques, the second conducting layer is masked, etched and defined to form a conducting line.
Conventional field programmable devices (FPDs) or antifuse structures typically draw a programming current of approximately 1 milliamp for a programming time of approximately 1 millisecond during programming when a standard programming voltage in the range of 15 to 30 volts is applied. These conventional devices typically have an off-resistance in the range of 10 mega to 10 gigaohms in the unprogrammed state and an on-resistance in the range of 10 to 10000 ohms.
The fabrication process for these devices has some disadvantages. For example, the dielectric antifuse layer may be etched during the pre-metal clean step included in standard CMOS processing. Also during the clean process, defects in the antifuse layer may be generated, which is one of the limiting factors in device yield.
Moreover, with the existing technology, the cost of manufacturing ROMs, PROMs and EPROMs is relatively high. The PROMs have a long access time and the EPROMs are manufactured by complicated process.